Instead of using traditional way to increase the critical charge required to flip a cross-coupled feedback mechanism, we presented a dynamic memory-based solution, lacking internal feedback, which utilizes CDMR and single-bit parity to achieve per-bit error detection and single bit error correction capabilities. The proposed 4T CDMR memory array was implemented in a 65-nm technology within a silicon footprint that is 47% smaller than a conventional 6-T SRAM bit cell and 2.5×–5× smaller than other state of- the-art radiation-hardened bit cells. In addition, the static power consumption of the proposed topology is more than 48% lower than the other soft-error tolerant bit cells across the entire operating range.
We have presented a 10T SRAM cell that reduces soft errors
by 98% and facilitates a differential read access. Differential
read is critical for easier design of the sense amplifier and for
reliable sense operation under the worst case conditions. The
high SNM of the proposed cell enables operating in sub-0.4 V
regime to save leakage power while offering better data stability
compared to the 6T cell as well as the DICE cell. In addition, the
cell can be used as a latch to design soft error robust register files
and flip-flops. Research along this line is currently in progress.


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